i ntegrated c ircuits d ivision www.ixysic.com ds-CPC3980-r02 1 CPC3980 n-channel depletion-mode vertical dmos fet bv dsx / bv dgx r ds(on) (max) i dss (min) package 800v 45 ? 100ma sot-223 applications features description ordering information circuit symbol ? normally-on switches ? solid state relays ? converters ? telecommunications ? power supply ? current regulators ? high breakdown voltage: 800v ? low on-resistance: 45 ? max. at 25oc ? low v gs(off) voltage: -1.4 to -3.1v ? high input impedance ? small package size: sot-223 package pinout d g d s 4 123 d s g part # description CPC3980ztr sot-223: tape and reel (1000/reel) the CPC3980 is an 800v, n-channel, depletion-mode, field effect transistor (fet) created using ixys integrated circuits division?s proprietary vertical dmos process. yielding a robust device with high input impedance, this process enables world class, high voltage mosfet performance with an economical silicon gate architecture. as with all mos devices, the fet structure prevents thermal runaway and thermal-induced secondary breakdown, which makes the CPC3980 ideal for use in high-power applications. the CPC3980 is a highly reliable fet device that has been used extensively in ixys integrated circuits division?s solid state relays for industrial and telecommunications applications. the CPC3980 is available in the sot-223 package.
i ntegrated c ircuits d ivision www.ixysic.com 2 r02 CPC3980 absolute maximum ratings are stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. absolute maximum ratings @ 25oc electrical characteristics @ 25oc (unless otherwise noted) parameter ratings units drain-to-source voltage 800 v gate-to-source voltage 15 v pulsed drain current 150 ma total package dissipation 1 1.8 w operational temperature -55 to +125 o c junction temperature, maximum +125 o c storage temperature -55 to +125 o c 1 mounted on 1"x1" 2 oz. copper fr4 board. parameter symbol conditions min typ max units drain-to-source breakdown voltage bv dsx v gs = -5.5v, i d =100a 800 - - v gate-to-source off voltage v gs(off) v ds = 15v, i d =1 ? a -1.4 - -3.1 v change in v gs(off) with temperature dv gs(off) /dt v ds = 15v, i d =1 ? a - - 4.5 mv/ o c gate body leakage current i gss v gs =15v, v ds =0v - - 100 na drain-to-source leakage current i d(off) v gs = -5.5v, v ds =800v - - 1 a saturated drain-to-source current i dss v gs = 0v, v ds =15v 100 - - ma static drain-to-source on-state resistance r ds(on) v gs = 0v, i d =100ma, v ds =10v --45 ? change in r ds(on) with temperature dr ds(on) /dt - - 2.5 %/ o c forward transconductance g fs i d = 50ma, v ds = 10v 100 - - m ? input capacitance c iss v gs = -3.5v v ds = 25v f= 1mhz - 115 -pf common source output capacitance c oss 5 reverse transfer capacitance c rss 3 source-drain diode voltage drop v sd v gs = -5v, i sd =150ma - 0.72 1 v thermal resistance junction to ambient ? ja - - 55 - oc/w junction to case ? jc - - 23 -
i ntegrated c ircuits d ivision CPC3980 www.ixysic.com 3 r02 *the performance data shown in the graphs above is typical of device performance. for guaranteed parameters not indicated in t he written speci? cations, please contact our application department. performance data @25oc (unless otherwise noted)* temperature (oc) -50 -25 0 25 50 75 100 125 v threshold (v) -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 threshold voltage vs. temperature (i d =1 p a, v ds =10v) temperature (oc) -50 -25 0 25 50 75 100 125 on-resistance ( : ) 20 30 40 50 60 70 on-resistance vs. temperature (i d =100ma, v gs =5v) temperature (oc) 0 20 40 60 80 100 120 140 power dissipation (w) 0.0 0.5 1.0 1.5 2.0 power dissipation vs. ambient temperature voltage (v) 0.1 1 10 100 1000 current (a) 0.001 0.01 0.1 1 forward safe operating bias (v gs =0, dc load) limited by device channel saturation limited by device r ds(on) v ds (v) 0246810 drain current (ma) 0 20 40 60 80 100 output characteristics v gs = -1 v gs = -1.2 v gs = -1.4 v gs = -1.6 i d (ma) 0 20 40 60 80 100 on-resistance ( : ) 20 25 30 35 40 on-resistance vs. drain current (v gs =0v) v gs (v) -2.5 -2.0 -1.5 -1.0 -0.5 i d (ma) 0 20 40 60 80 100 120 input admittance (v ds =10v) 85oc 55oc 25oc -40oc i d (ma) 0 20 40 60 80 100 g m (ms) 0 50 100 150 200 250 300 transconductance vs. drain current (v ds =10v) -40oc 25oc 55oc 85oc v ds (v) capacitance (pf) capacitance vs. drain-source voltage (v gs =3.5v) 0 5 10 15 20 25 30 1 10 100 1000 c iss c rss c oss
i ntegrated c ircuits d ivision www.ixysic.com 4 r02 CPC3980 manufacturing information moisture sensitivity all plastic encapsulated semiconductor packages are susceptible to moisture ingression. ixys integrated circuits division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . device moisture sensitivity level (msl) rating CPC3980z msl 1 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. device maximum temperature x time CPC3980z 260oc for 30 seconds board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. cleaning methods that employ ultrasonic energy should not be used.
i ntegrated c ircuits d ivision for additional information please visit our website at: www.ixysic.com 5 CPC3980 ixys integrated circuits division makes no representations or warranties with respect to the accuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity a re expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and conditions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infri ngement of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits division reserves the right to discontinue or make changes to its p roducts at any time without notice. specification: ds-CPC3980-r02 ?copyright 2015, ixys integrated circuits division all rights reserved. printed in usa. 4/10/2015 mechanical dimensions CPC3980z CPC3980ztr tape & reel dimensions mm min / mm max (inches min / inches max) 6.705 / 7.290 (0.264 / 0.287) 0.229 / 0.330 (0.009 / 0.013) 0.914 min (0.036 min) 1.90 (0.075) 1.90 (0.075) 6.10 (0.24) 2.286 (0.090) 0.90 (0.035) 3.20 (0.126) 6.30 / 6.71 (0.248 / 0.264) 2.286 (0.090) 3.30 / 3.71 (0.130 / 0.146) 2.90 / 3.10 (0.114 / 0.122) 0.610 / 0.787 (0.024 / 0.031) 0.020 / 0.102 (0.0008 / 0.004) 0.864 / 1.067 (0.034 / 0.042) 4.597 (0.181) 1.549 / 1.803 (0.061 / 0.071) 1.499 / 1.981 (0.059 / 0.078) pcb land pattern pin 1 dimensions mm (inches) embossment embossed carrier 177.8 dia (7.00 dia) top cover tape thickness 0.102 max (0.004 max) w=12.08 0.2 (0.476 0.008) b 0 =7.42 0.1 (0.292 0.004) a 0 =6.83 0.1 (0.269 0.004) p=8.03 0.1 (0.316 0.004) k 0 =1.88 0.1 (0.074 0.004) 2.00 0.05 (0.079 0.002) 4.00 0.1 (0.157 0.004) 1.75 0.1 (0.069 0.004) 5.50 0.05 (0.217 0.002)
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